瑞斯克石英晶體振蕩器說明書，隨著電子行業的產品越來越多元化，為了更好順應市場的變化，Crystek公司利用自身的優勢，針對目前振動器產品進行深入研究與探索說明，并研發設計出極具有價值的石英晶體振蕩器，并因此吸引了廣泛用戶的關注，產品融合的高質量低抖動低電壓的特點，可以滿足不同應用程序的需求，同時也優化相噪聲，又獲得極好的用戶體驗。

圖1中的皮爾斯門振蕩器得到了大多數設計師的認可，但很少有人了解如何正確指定晶體。拓撲結構中使用的晶體圖1可以是基本的AT-CUT或BT-CUT。BT-CUT晶體質量差與AT-CUT相比，頻率隨溫度的穩定性。此拓撲使用平行晶體而不是串聯晶體。當指定平行晶體時，晶體制造商還將要求您指定負載電容。

要了解負載電容，請考慮串聯LC電路，其中晶體是L，負載電容是C。諧振LC電路的頻率將作為L和C的函數而變化在晶體情況下，L是固定的（溫度不是參數）。瑞斯克石英晶體振蕩器說明書.

晶體數據表上的參數由負載電容是25°C時中心頻率的公差或校準。如果有源晶體振蕩器電路設計不匹配負載電容值，則中心頻率將不在數據表的公差限制。有趣的是并聯晶體要求其電容負載有效串聯其端子。
那么，您的皮爾斯門振蕩器向結晶如圖2所示的一個簡單計算將告訴您。

圖2中大多數設計師忽略的最重要的事實是反相器門的內部輸入和輸出電容。這些與外部（C1和C2）相比在值上是顯著的。如果Cin和Cout沒有指定，那么每個5 pF的猜測值是好的開始以后可以通過改變啟動來優化電路C1和C2的值。所以，不要放棄你的主要寬容；計算您的振蕩器電容負載。

既然你知道了如何計算負載電容電路呈現給水晶，您應該選擇什么負載電容？在回答這個問題之前，你需要知道晶體中心頻率對負載的靈敏度電容。這被稱為微調靈敏度S，由下式給出：

其中Cm是晶體的運動電容，
Co是晶體的分流電容，
Cload是負載電容。
從修剪靈敏度方程中，你可以看到，你制作的Cload越小，就越大微調靈敏度。換句話說，如果你正在設計一個固定頻率的時鐘，那么你選擇一個高的Cload值，比如20 pF。但是，如果你正在設計一個可變頻率振蕩器（VCXO）選擇諸如14pF的低Cload值。瑞斯克石英晶體振蕩器說明書.

The Pierce-gate oscillator of Figure 1 is well recognized by most designers, but few Tunderstand how to specify the crystal correctly. The crystal used in the topology of Figure 1 can be either a fundamental AT-CUT or BT-CUT. A BT-CUT crystal has poor frequency stability over temperature compared to an AT-CUT. This topology uses a parallel crystal and not a series crystal. When a parallel crystal is specified, the crystal manufacturer will also require that you specify a load capacitance.

To understand load capacitance, think of a series LC circuit where the crystal is the L and the load capacitance is the C. The resonance frequency of the LC circuit will vary as a function of L and C. But in the crystal case, the L is fixed (temperature not being a parameter).

The parameter on the crystal data sheet that is controlled by the load capacitance is the tolerance or calibration of the center frequency at 25°C. If the oscillator circuit is not designed to match the load capacitance value, then the center frequency will not be within the tolerance limits of the data sheet. Interestingly enough, a so-called parallel crystal requires its capacitive load effectively be in series with its terminals.

So what load is your Pierce-gate oscillator presenting to the crystal? A simple calculation illustrated with Figure 2 will tell you.

Cload = {[Cin+C1][C2+Cout]/[Cin+C1+C2+Cout]} + pcb strays (2~3pF)

Example: Let Cin = Cout = 5pF

; C1 = C2 = 20pF Therefore, Cload = {[25][25]/[25+25]} + 3

= 12.5 + 3 = 15.5pF Select Cload = 16pF
The most important fact in Figure 2 that most designers neglect is the internal input and output capacitance of the inverter gate. These are significant in value compared to the external (C1 and C2). If Cin and Cout are not specified, then a guess value of 5 pF for each is a good start. The circuit can be later optimized by changing the starting values of C1 and C2. So don’t throw away your major tolerance; calculate your oscillator capacitive load.

Now that you know how to calculate the load capacitance the circuit presents to the crystal, what load capacitance should you choose? Before answering this question, you need to know the sensitivity of the crystal center frequency vs. load capacitance. This is known as the trim sensitivity S and is given by:

S C C C m o load = − + ⋅ − 2 10 2 6 ( ) in ppm/pF

where Cm is the motional capacitance of the crystal,

Co is the shunt capacitance of the crystal,

and Cload is the load capacitance.

From the trim sensitivity equation you can see that the smaller you make Cload, the larger the trim sensitivity. In other words, if you are designing a fixed frequency clock, then you choose a high Cload value like 20 pF. However, if you are designing a variable frequency oscillator (VCXO), choose a low Cload value such as 14 pF.

The C1 and C2 values also affect the gain of the oscillator. The lower the values, higher the gain. Likewise, C2/C1 ratio also affects gain. To increase the gain, make C1 smaller than C2.

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